Technology
Full-custom methodology
Nine stages, each one latched before the next begins, with evidence a customer can read.
Where it pays offWhere a few cell types repeat very many times and carry enough of a chip's energy or area to move the whole chip.
When to use it
A choice made block by block.
Full-custom applies to the critical datapath blocks. The rest of a chip uses a standard tool flow. Which block gets which treatment depends on where its energy and area actually go.
Transistor-level design
Cells designed for this chip, with transistor-level layout and wiring, wrapped as a characterized block. For the critical datapath blocks that carry the chip's energy or area.
Project-specific cells
A foundry library plus a few cells made for the project, mixed among synthesised logic. For blocks that gain from a few better cells.
Synthesis
A standard-cell library with automated synthesis and place and route. For control logic, interfaces and the rest of the chip, and as the baseline every custom block is measured against.
Schematic, layout, extraction and sign-off tools run at every step of transistor-level design.
How a design moves to siliconTransistor-level design pays off most when all five hold.
- A small number of cell types repeat a very large number of times.
- Those cells carry enough of the chip's energy or area to move the chip-level metric.
- The function is stable enough that the layout will not be redone.
- A synthesised baseline exists on the same process to measure against.
- The project can afford characterization and silicon correlation.
In other cases, project-specific cells or synthesis are usually the more efficient choice.
The method
Nine stages, each latched before the next.
A pipeline stores each stage's result in a register before the next stage may use it. This method treats evidence the same way. A stage closes when its evidence exists and a customer can read it.
Fit and partitioning
Decide block by block what gets transistor-level design, what uses project-specific cells and what stays synthesised, based on where energy and area actually go.
Evidence a customer should expect
- A partition table with each block's share of area and power, and the reason for its design style
- A synthesised baseline for every block proposed as custom
Architecture and datapath definition
Fix the pipeline depth, bit-slice structure, clock scheme and supply target before any cell is drawn.
Evidence a customer should expect
- An executable reference model and test vectors
- A delay, energy and area budget for each bit slice, with its assumptions stated
- The list of sign-off corners
Circuit and cell design
Design latches, flip-flops and adders at transistor level, choosing fin counts and threshold types.
Evidence a customer should expect
- Schematics
- Pre-layout SPICE across corners, covering setup, hold, retention and noise margin
- Monte Carlo statistics
- A comparison with the equivalent foundry library cell
Layout on foundry rules
Draw cells and bit slices on the foundry's grid and patterning rules, with pin access planned for the router.
Evidence a customer should expect
- Clean DRC, LVS and ERC logs, with tool and deck versions
- Colouring and density results
- Every waiver listed, with its reason
Extraction and post-layout simulation
Extract resistance and capacitance from the real layout and simulate again, so results reflect the layout rather than the schematic.
Evidence a customer should expect
- A pre-layout against post-layout table for delay and energy
- The parasitic corners used
- A record of the layout changes made in response
Library characterization and models
Produce the timing, power, physical and functional views a digital flow needs.
Evidence a customer should expect
- Liberty files with the current-source and variation data the flow requires
- A LEF abstract and a behavioural model
- A QA report comparing the models with SPICE, with sample size and error distribution
Integration with clock and power
Place the custom blocks in the chip and design clock and power delivery around them.
Evidence a customer should expect
- Skew and jitter budgets and results
- Static and dynamic IR drop reports
- EM reports at stated activity and temperature
- Hierarchical timing using the delivered models
Verification and sign-off
Show that the schematic implements the RTL, then run full foundry sign-off with margins for variation and aging.
Evidence a customer should expect
- An equivalence report between RTL and schematic, with its scope and exclusions
- Timing at sign-off corners, with variation
- An aging and self-heating margin report
- A signed tape-out checklist
Silicon correlation
Measure real silicon, compare it with the models, and feed the differences back into the libraries and margins.
Evidence a customer should expect
- On-chip monitor data
- Shmoo plots and Vmin distributions across wafers and process corners
- A measured against modelled table, with sample size
The drawings illustrate the kind of evidence at each stage. Foundry-derived evidence is shared under NDA where the foundry's agreement requires it.
Full-custom services
What we have done
Two tape-outs on TSMC 16 nm FinFET.
From a multi-project wafer to a full mask set, the full-custom method was applied on real silicon.
88cores
Multi-project wafer (shuttle)
November 2018
200cores
Full mask set
June 2019
Operating voltage on the shuttle samples
Shuttle samples measured at
0.36 V
Well below the process's nominal core voltage.
The compute core was full-custom; the rest of each chip used a standard tool flow.
What the work covered
Custom cells
Custom multi-bit flip-flops and adders were used in the compute core.
Low-voltage libraries
Foundry cell libraries were re-characterized for low voltage (re-characterization).
Hand placement
The compute core was placed by hand.
Abutment
Core sub-blocks were abutted without boundary cells, at 95% placement utilisation at tape-out.
Sign-off
Timing and IR drop were signed off across multiple corners.
Bring-up
Bring-up was done by our team, with outside packaging and analysis partners.
Silicon feedback
Measurements on the full-mask silicon fed into the follow-on design, refining cell choice and hold margin for dynamic logic at ultra-low voltage.
7 nm and 6 nm
As a TSMC direct account, we are authorised for 7 nm FinFET design and have carried out 6 nm AI full-custom chip design for a top AI customer.
Process nodesIntellectual property
Patents and registered layout designs
CN111308329B
Chinese invention patent
Test and binning of many-core chips.
CN111294045B
Chinese invention patent
Reducing phase noise in charge-pump phase-locked loops.
BS.185572790BS.195600134
Registered layout designs
Integrated-circuit layouts registered in the company's name.
A block that could benefit?
Send its specification and where its energy and area go, and we will reply.