Company
Leadership
Chipchain has been led from Shenzhen since it was founded there in 2018.
- Full-custom AI chipsFull-custom design for AI inference, training, large model, edge and vision chips
- Custom AI siliconApplication-specific AI accelerators, from architecture to tape-out
- Edge AI systemsCompute modules and systems built around AI silicon
- Full-custom designTransistor-level design for critical datapath blocks
- Library characterizationStandard cell library characterization and re-characterization, including ultra-low voltage
- Hand-crafted netlistsCustom gate-level netlists, designed with custom cells and hand placement
- Custom clock treesClock distribution designed for pipelines and regular arrays
- Manual place and routeHand placement, custom clock trees and abutment
- Standard cell librariesCells tuned for power, performance and area
- ASIC designArchitecture, RTL, verification, DFT and physical design
- Production and supply chainWafers, test, assembly and logistics under one plan
- Engagement modelsSpec-in, netlist-in, GDS-in or production transfer
- Full-custom methodologyWhen transistor-level design is worth it, and the nine stages of the method
- Process nodesThe FinFET nodes we have designed on
- Design methodologyHow a design moves from specification to silicon
- GlossaryPlain-language definitions of chip-design terms