Design services
Hand-crafted gate-level netlists.
Chipchain has the capability to design hand-crafted netlists and can tailor this service to your project. For regular, pipelined datapaths, we map RTL directly to custom cells as a gate-level netlist, so the netlist, the cells and the placement are optimised as one.
- Best for
- Pipelined compute logic with high switching activity
- Method
- RTL mapped to custom cells, with the gate-level netlist generated by script
- Works with
- Custom cells, library characterization and manual place and route
- Verification
- Formal equivalence with the RTL, gate-level simulation and static timing analysis
Why a hand-crafted netlist
Netlist, cells and placement designed together.
Mapping to custom cells
The RTL is mapped by hand to custom registers, latches and combinational cells.
Regular structure
Pipeline stages share a structure, and the netlist is organised in bit slices that match the placement.
Consistent naming
A consistent naming scheme makes the netlist easy to script and to place by hand.
Critical-path optimisation
Cell type, drive strength and threshold type are chosen for the critical paths.
Sequential logic
Multi-bit registers and dynamic cells lower the power of the clock and sequential logic.
Compatible with automated flows
Logic outside the custom part stays in the synthesis flow, and everything closes in one sign-off.
The netlist flow
Six steps, from RTL to a netlist ready for placement.
RTL review
Module hierarchy and data flow confirmed, and the logic suited to custom design identified.
Cell selection
Cell types chosen for registers, latches and combinational logic.
Netlist generation
RTL mapped to custom cells, with the gate-level netlist generated by script.
Equivalence check
Formal verification that the netlist matches the RTL.
Gate-level simulation and timing
Gate-level simulation and static timing analysis.
Hand-off to placement
The netlist and its naming scheme go to manual place and route.
Questions about hand-crafted netlists
Why use a hand-crafted netlist?
It maps RTL according to the custom cells, and its consistent naming makes it easy to script and to place by hand. The netlist and the placement then work closely together.
Which logic suits a hand-crafted netlist?
Pipelined compute logic with high switching activity suits it best. Control logic has complex paths and usually stays in the synthesis flow.
Do we need to write the netlist ourselves?
For typical pipelined logic we can produce it from your RTL. For complex designs we work with your team, by project.
What does this need from the RTL?
Clear module hierarchy and data flow, so that scripts can process it through to the netlist.
How is the netlist checked?
Formal equivalence confirms that it matches the RTL, followed by gate-level simulation and static timing analysis.
Related pages
Have a block that suits a hand-crafted netlist?
Send the RTL structure, the target process and the timing target, and we will reply.