Design services
Standard cell library characterization.
Library characterization turns a cell's circuit and layout into the models that synthesis, place and route and static timing analysis use. We provide characterization and re-characterization services, including ultra-low-voltage libraries.
- Services
- Library characterization, re-characterization and custom-cell characterization
- Models
- Timing, power and noise models in Liberty format: NLDM or CCS, with LVF variation data where sign-off needs it
- Deliverables
- Library views such as Liberty, LEF and Verilog, and a quality report comparing the models with SPICE
- Our work
- Cell libraries on 16 nm FinFET re-characterized to ultra-low voltage, across 54 corners from 0.30 V to 0.48 V
What we do
From cells to a library ready for sign-off.
Library characterization
Timing, power, noise and constraint models for custom and new cells. The settings match the foundry cells', so both sign off together.
Re-characterization
Models extracted again from a foundry library at your voltages and corners, covering the conditions the design really runs in.
Ultra-low-voltage libraries
Libraries for ultra-low-voltage design, with a focus on the accuracy of timing, power and noise models at low voltage.
Custom cells
Flip-flops, latches and adders designed for the application and characterized in the same flow.
Calibration against circuit simulation
For dynamic cells and cells that need high accuracy, detailed circuit simulation calibrates the timing and power values in Liberty.
Quality checks
Models compared with SPICE, library files checked for consistency, and a quality report.
The library characterization flow
Six steps, from cell list to delivery.
Requirements
The cell list, corners, voltage range, model types and accuracy targets.
Set-up
SPICE models and extracted netlists, and the indexes for input transition, output load and constraints.
Simulation and extraction
Simulation across the corners, extracting timing, power, noise and constraints.
Calibration
Detailed circuit simulation of key cells, and calibration of the models.
Quality checks
Models compared with SPICE, and library files checked for consistency.
Delivery
Library views and a quality report. After silicon, margins can be calibrated to measurements.
Library characterization terms
- Library characterization
- Each standard cell is simulated across process, voltage and temperature conditions to extract timing, power and noise models.
- Re-characterization
- Re-characterization. Models are extracted again from a foundry library for a new voltage, corner or model, for example to extend the library to ultra-low voltage.
- Corners (PVT)
- Combinations of process, voltage and temperature. A library needs models at every combination used in sign-off.
- Liberty (.lib)
- The standard library format that synthesis, place and route and static timing analysis read.
- NLDM and CCS
- Two kinds of timing and power model. NLDM records delay and transition in tables. CCS models current-source waveforms, which suits advanced processes and low voltage better.
- LVF
- Liberty Variation Format, which adds delay statistics from process variation to the library, for static timing analysis that includes variation.
Questions about library characterization
What is the difference between characterization and re-characterization?
Characterization extracts complete models starting from a cell's netlist. Re-characterization extracts them again from an existing library for a new voltage, corner or model.
Can custom cells sign off together with foundry cells?
Yes. Custom cells use the same characterization settings as the foundry cells and sign off in the same flow.
How do custom cells enter the digital back-end flow?
In two ways. The custom part can be hardened into a block, or a placement script can fix the custom cells while the rest follows the automated flow.
How do you keep models accurate at ultra-low voltage?
Low-voltage accuracy rests on detailed circuit simulation. We compare the simulation with the library, write simulated values into it where needed, and calibrate margins to silicon measurements.
Which files do you deliver?
Library views such as Liberty, LEF and Verilog, and quality reports. Characterization scripts and other files are agreed by project and under the foundry's agreement.
Related pages
Need library characterization or re-characterization?
Tell us the process, the number of cells, the voltage range and the corners, and we will reply.