Design services
Custom clock tree design.
Chipchain has the capability to design custom clock trees and can tailor this service to your project. We design clock distribution around the structure of pipelines and regular arrays, so clock power, skew and timing are optimised together.
- Covers
- Clock structure, clock buffers, clock routing, and skew and jitter budgets
- Best for
- Pipelined datapaths, MAC arrays and many-core compute blocks
- Works with
- Custom cells, multi-bit registers, hand-crafted netlists and manual place and route
- Verification
- Skew and jitter analysis, static timing analysis and clock power analysis
What a custom clock tree does
The clock and the datapath designed together.
Structure
Clock trunks and branches planned around the pipeline and array, matching the placement.
Lower clock power
Multi-bit registers share one clock pin and its internal clock inverters across several bits, so the tree drives fewer sinks: lower clock load and switching power.
Skew and jitter
Symmetric routing over a regular structure controls clock skew, and a short, matched buffer chain limits the jitter the tree adds.
Setup and hold balance
The clock is arranged with the direction of data flow, balancing setup and hold paths.
Multi-phase clocks
A latch-based design can use three-phase non-overlapping clocks: the latches allow time borrowing between stages, and the non-overlap makes hold time easier to meet.
Integration with automated flows
A custom block gives the top level its clock interface and models, while the top level keeps tool-based clock tree synthesis.
The clock tree flow
Six steps, from clock requirements to sign-off.
Requirements
Frequency, voltage, skew and jitter budgets, and the clock power target.
Structure
The clock structure and sequential cells chosen, with trunks and branches planned.
Buffers and routing
Clock buffers placed, and clock routing completed by rule.
Extraction and simulation
Parasitic extraction, and simulation of skew, jitter and clock power.
Timing analysis
Static timing analysis across corners, with iteration.
Sign-off and integration
The clock interface and models delivered to the top level, and sign-off completed.
Questions about custom clock trees
How does a custom clock tree differ from a tool-generated one?
Clock tree synthesis (CTS) in a tool suits irregular logic such as control logic and interfaces. A custom clock tree is designed around the structure of a pipeline or regular array, for a better balance of power, skew and timing.
Which blocks suit a custom clock tree?
Blocks with many registers, a regular structure and high switching activity, such as pipelined datapaths and MAC arrays. The more registers, the greater the gain.
Can it work with an automated flow?
Yes. A custom block gives the top level its clock interface and models, and the top level keeps tool-based clock tree synthesis.
Can you design a custom clock tree for our project?
Yes. We can take it on by itself, or together with hand-crafted netlists and manual place and route.
Related pages
Need a custom clock tree?
Send the block's structure, target frequency, target process and clock power target, and we will reply.