Technology

Chip design, in plain language.

The terms this site uses, from ASIC to yield, each explained in a sentence or two.

Terms

ASIC: An application-specific integrated circuit, a chip designed for one product or task rather than for general use.
Fabless: A chip company that designs its chips and has them manufactured by a foundry.
Foundry: A company that manufactures chips designed by others.
Process node: A generation of a foundry's manufacturing technology. Nodes are named in nanometres, but the name no longer measures any single feature of the chip.
FinFET: A transistor whose channel is a thin vertical fin, wrapped by the gate on three sides. It leaks less than the older flat transistor.
Design kit (PDK): The foundry's process design kit, the rules, device models and libraries a chip is designed against.
RTL: Register-transfer level, the description of a chip's logic in a hardware language such as Verilog.
Verification: Showing, by simulation and formal methods, that the RTL does what the specification says.
Synthesis: Turning RTL into a netlist of standard cells.
Netlist: The list of cells in a design and the connections between them.
Standard cell: A small, pre-designed circuit such as a gate or a flip-flop, from which synthesised designs are built.
Library characterization: Simulating standard cells across process, voltage and temperature conditions to extract timing, power and noise models.
Re-characterization: Re-characterization: extracting a foundry library's models again for a new voltage, corner or model.
Full-custom design: Designing circuits and layout at transistor level, for the blocks that decide a chip's metrics.
Hand-crafted netlist: A gate-level netlist mapped from RTL to custom cells, rather than through a synthesis tool's general mapping.
Manual place and route: Engineers, rather than tools, decide the cell positions and wiring of key blocks.
Custom clock tree: A clock distribution designed around the structure of a pipeline or regular array, rather than generated by clock tree synthesis in a tool.
Design for test (DFT): Structures added to a chip so that every manufactured part can be tested.
ATPG: Automatic test pattern generation, software that creates the patterns used in production test.
BIST: Built-in self-test, circuitry that lets a block, usually a memory, test itself.
Physical design: Turning a netlist into a layout, through floorplanning, placement, clock tree and routing.
Sign-off: The final checks of timing, power and physical rules before a design is released.
GDSII: The file format in which a finished layout is handed to the foundry.
Tape-out: Releasing a finished design to the foundry for manufacture.
Multi-project wafer (MPW): A shared run in which several designs share one mask set and its cost.
Mask set: The photomasks that pattern each layer of a design on the wafer. A full mask set is made for one design alone.
Wafer probe: Testing every die on a wafer before the wafer is cut, also called chip probing (CP).
Final test: Testing packaged parts against the specification (FT).
Yield: The share of manufactured dies or parts that pass test.
NPU: A neural processing unit, an accelerator for the arithmetic of neural networks.
SRAM: Static RAM, the fast memory built into the chip itself.
HBM: High-bandwidth memory, stacked DRAM placed beside a processor in the same package.
Chiplet: One of several dies combined in one package to work as one chip.
Interposer: A layer of silicon or organic material that connects chiplets and memory inside a package.